As is well known, a phase-locked loop system produces an output signal which tracks an input signal in frequency and exhibits a fixed phase relationship to the input signal. As the input signal changes in frequency, the output signal likewise changes in such a manner as to maintain the phase relationship between the input and output signals. Originally, phase-locked loops were implemented using only analog techniques. These techniques continue in use today in many data processing and communications systems. An analog phase-locked loop typically consists of four fundamental parts; namely, a phase detector, a charge pump, a filter and a voltage controlled oscillator (VCO).
The phase detector is a device which detects the difference in phase between two input signals, and produces an output signal based thereon. In a phase-locked loop the two inputs to the phase detector are the input to the phase-locked loop and the output signal of the VCO, i.e., the output of the phase-locked loop. The output signal from the phase detector is a digital up/down signal, hereinafter referred to as an error signal. The charge pump produces a source/sink charge current based on the direction of this error signal and the magnitude of a received, fixed reference current. The charge pump outputs the charge current to the filter for establishing a control voltage there across. The filter's control voltage is applied to the input of the VCO. The filter serves to remove any high frequency components from the charge current produced by the charge pump and provides a slowly varying output signal which is representative of the average error in phase between the output signal and the input signal.
The voltage controlled oscillator generates an output signal having a frequency corresponding to the slowly varying control signal across the filter. In one conventional embodiment, the voltage controlled oscillator comprises a voltage to current converter which is coupled through a summing node to an oscillator that provides the output signal from an input current. A fixed bias current is also fed to the summing node. The fixed bias current operates to moderate the gain characteristics of the VCO.
Due to feedback of the output signal to an input of the phase detector, the frequency of the voltage controlled oscillator is adjusted by the VCO input signal, i.e., the control signal across the filter, to maintain the fixed relationship between the input signal and output signal of the PLL.
Component tolerances and process variations often result in a wide range of possible frequency responses at the VCO output of an analog phase-locked loop system. Various PLL calibration techniques are known in the art. For example, center frequency calibration of the output signal is traditionally accomplished by trimming the value of a resistor(s) within the VCO. Unfortunately, this is a difficult and expensive operation, and requires use of circuits which are very temperature stable and insensitive to power supply variations. The gain of a phase-locked loop can also vary significantly with process, temperature and power supply variations. Further, due to technology advances, PLLs are today required to produce higher frequencies while VCO transfer function tolerances become more critical and less achievable simultaneously.
A preferred PLL calibration approach is described in a co-pending application entitled "Calibration Systems and Methods for Setting PLL Gain Characteristics and Center Frequency," Ser. No. 08/173,454, filed Dec. 23, 1993, assigned to the same assignee as the present application, and the entirety of which is hereby incorporated herein by reference. Along with describing a calibration system and method for establishing an analog PLL with zero tolerance center frequency, the co-pending application presents techniques for minimizing VCO gain deviation across the transfer function.
It has been further observed that a PLL's loop damping factor can deviate with the filter components, the gain of the VCO, the charge pump output current, along with process, temperature and power supply variations within a given frequency range. These variations lead to PLL instability which may be intolerable in a particular system design. In addition, as PLL frequency increases, a PLL's damping factor typically declines significantly.
Presently, the PLL damping factor is fixed at time of circuit fabrication by controlling the magnitude of the charge current supplied by the charge pump through a physical trimming of external resistors through which the fixed reference current is supplied to the charge pump. This is successful because the amplitude of the charge pump's source/sink charge current to the filter is proportional to the reference current provided thereto. Such a physical "trimming" approach, however, has the same drawbacks noted above in connection with the conventional "static" technique for trimming resistors within the VCO to set the output signal's center frequency and/or gain.
Thus, a novel, closed-loop calibration technique for periodically, dynamically and precisely controlling an analog PLL's loop damping factor over a wide range of frequencies is needed. Such a calibration technique would allow analog PLL components to be integrated onto a single chip while still retaining good loop stability.